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Cadence
University Program Member
Abbreviated
Research Project Descriptions
Project:
Low-power RF Design
Saeed
Yasami
I am currently a Ph.D. candidate in the
VLSI research Group. My research interest is focused on
low power RF and mixed-signal VLSI system and emerging
technologies.
Tools:
Cadence (Virtuoso Schematic and Layout Editor, Spectre)
Project:
Low-power high-density SRAM Cell
Wei Shu
The CACS VLSI research group has over the years proposed various SRAM architectures for
low-voltage operation. The intent of this project is to bring those concepts up to speed with
recent technologies and potentially merge them together or with ideas such as Macrocells.
Tools:
Cadence (Encounter, Virtuoso Schematic and Layout Editor, Spectre)
Project:
Green ALU
Mazen Al Haddad
Design of an ALU with lower power consumption due to novel MUX chaining and ordering.
With an increasing number of ALU functions, the efficient MUX placement delivers even more power saving.
Designing on Layout level and schematic level.
Tools:
Cadence (Virtuoso Schematic and Layout Editor, Spectre)
Project:
ASIC Design for a Compression Method Based on Random Filters
Mohamed Shaban
Natural signals often contain some type of structure that makes them compressible. That is
compressible signal of length N can be represented by S samples only such that S << N. The
usual approach for compressing discrete time signals (e.g. image) is to transform the signal into
its basis (e.g. Dirac basis) and then apply a non linear algorithm. These methods are called
transform coders (e.g. JPEG). This approach is not practical if the signal is presented at a high
rate or if the measurement device has limited computational resources.
As a result, Candes, Romberg, Tao and Donoho have proposed an approach, known
as Compressed Sensing (CS), in which a random linear projection is used to acquire efficient
representations of compressible signals directly. For discrete time signals, CS is not suited to
real-time applications or large data sets because the measurement process requires access to the
entire signal at once; the measurements are not time-invariant and the reconstruction algorithms
are very expensive.
As solution for this problem, random filters were introduced. In fact, the random filter
mainly works by convolving finite-length, discrete-time signal f with a random-tap FIR filter h
and then downsampling the filtered signal to obtain a compressed representation y. Two different
methods for signal acquisition that take full advantage of the structure of the random filter were
introduced. The first method for calculating the measurements, performs linear convolution and
downsampling simultaneously. However, the second method uses FFTs to calculate the
convolution. This project aims at providing ASIC design for the second method realized using FFTs.
Tools:
Cadence (Encounter, Virtuoso Schematic and Layout Editor)
Project:
Analyzing FinFET SRAM Circuits
Anandi Dutta
In this project, the analysis of different types of
SRAM circuits would be done. The read noise margin, write noise margin,
ratio of on-current/off-current would be explored. The independent gate
structured FinFET and multiple gate structured gate FinFET will be
simulated.
Tools:
Cadence (Encounter, Virtuoso Schematic and Layout Editor, Spectre)
Project:
Green VLSI
Zaghloul ElSayed
Design and analysis of varies VLSI layouts with lower power consumption
due regarding the total process staring from the manufacturing phase, till
the operation phase.
Tools:
Cadence (Encounter, Virtuoso Schematic and Layout Editor, Spectre)
Project:
A Partitioning Algorithm for Multi-Stage Phase-Damped Power Gating
Salim
Farah (Alumni)
Ground bounce noise reduction in power-gated circuits: This work targets
the current rush experienced during power-gating by expanding on a
technique called "Staggered-Phase Damping" by introducing multiple
turn-on stages and partitioning optimization. Considering the increasing
reliance on power-gating for dealing with leakage power, solving the
resultant noise problem using limited resources is of high importance.
Tools:
Cadence (Virtuoso, Encounter, Spectre)
Project:
Application Specific SRAM memory design
Abhijit
Sil (Alumni)
Working on a subthreshold 6T
SRAM cell, designed to be operated at supply voltage as
low as 170mV with moderate noise margin, a subthreshold
7T SRAM cell, designed to be operated at supply voltage
as low as 220mV with high noise margin, and a High Speed
8T SRAM, a dual port SRAM designed for high speed cache
application. Also working on Single-ended Pseudo
Differential Sense Amplifier, a novel sense amplifier
implemented and to be used with above mentioned single
read bit memory cell. The design assures high access
speed which is comparable with conventional differential
sense amplifier.
Tools:
Cadence (Virtuoso schematic/layout, Encounter, and
Spectre)
Project:
VLSI Implementation of Image Registration and Fusion
Schemes
Milad
Ghantous (Alumni)
The project focuses on
low-power, low-computation VLSI architectures for image
registration and fusion, focusing on discrete complex
transforms designs as well as complex wavelet
transforms.
Tools:
Matlab, Cadence (Encounter, Virtuoso)
Project:
Linearization of Wireless Power Amplifiers
Mike
Talley (Alumni)
The focus of my research the development
of linearization techniques for non linear efficient
class E (switching) wireless power amplifiers. Current
wireless standards and modulation techniques require
highly linear power amplification. Unfortunately the
downside of this is the large power consumption required
by linear amplifiers. By implementing techniques to
linearize in the analog domain, power consumption can be
minimized therefore prolonging battery life in wireless
devices.
Tools:
Cadence (Spectre-RF, GoldenGate, RF-DE, Virtuoso)
Project:
Scalable Multi-core Design
Azeez
Sanusi (Alumni)
This is the most recent aspect of my
research, I explore the design methodologies that
guarantee high performance for highly scalable
multi-core systems intended for large scale parallel
computations (or scientific computations that are said
to be massively or embarrassingly parallel). I explore
these designs from the Network-on-chip (NoC) viewpoint,
since the NoC has been generally accepted and adopted as
the interconnect fabric that can support large scale
systems that would otherwise be unrealizable with the
traditional bus-based interconnect. Specifically, I
investigate the design of the memory hierarchy for
MPSoC's with distributed memory architectures on the NoC
platform and also investigate the design of various
hardware support for scalable primitives that will
ensure memory consistency and cache coherence and
synchronization in these networks.
Tools:
Cadence (Verilog, Encounter, Virtuoso)
Project:
Digital Ultrawideband Transmitter
Jared
Tessier (Alumni)
I am
building a mostly digital multi-phase ultra-wide-band
transmitter. Some of the notable features of the
architecture is a novel relaxation oscillator capable of
low voltage operation. Also level converting XOR gates
are used at the power amplifiers to double the effective
operational frequency. The design takes inherits many
techniques from the SERDES state of the art.
Tools:
Cadence (Virtuoso Schematic and Layout Editor, Encounter, Spectre)
Project:
Analog-to-Digital Converters for Ultra Wide Band (UWB)
Applications.
Mohamed
Shaker (Alumni)
Ultra-wideband radio needs high
sampling rates of at least 500 MS/s. The flash
architecture was always the primary choice for this kind
of applications but its exponential dependance on
resolution limits its capabilites. The time-interleaved
successive approximation regsiter architecture has
received a great interest in this decade as a perfect
alternative since it requires a linear number of
comparisons. This project aims to embed a novel clock
gating technique in a time-interleaved SAR design to
achieve the maximum possible power savings.
Tools:
Cadence (Virtuso Schematic and Layout Editor, Spectre, Verilog-XL, Encounter)
Project:
MPEG-2 to H.264/AVC enhanced transcoding
Tarek El Arabi (Alumni)
Design and optimize a hardware architecture for real-time intra-prediction algorithms for
MPEG-2 to H.264/AVC transcoders. The design should allow for faster, more power efficient real time MPEG-2
to H.264 transcoders, ideal for media streaming.
Tools:
Cadence (Encounter)
Project:
Parallel ECC Architecture
Esmail Amini (Alumni)
Designing a parallel, power-efficient and scalable word-based crypto architecture for scalar
point multiplication including add, multiplication and inversion operations on GF(2m) operands.
The architecture might be used for various operand sizes without modifying or reconfiguring the
underlying hardware. Besides, the architecture has the ability to perform several different operations in
parallel when each operation requires a small key size which significantly increases the overall performance
and throughput of the system.
Tools:
Cadence (Encounter)
Project:
SRAM Sense Amplifiers / CAVLC Decoder
Eswar
Kolli (Alumni)
Implementation of CAVLC decoder
for H.264/MPEG4AVC standard. Sense amplifiers for SRAM.
Tools:
Cadence (Verilog-XL, Encounter, Virtuoso Schematic and
Layout Editor, Spectre)
Project:
Low Power Huffman Decoders
Jason
McNeely (Alumni)
In applications such as video
processing and image processing, compression is needed
for storage and transmission. Variable length codes
allow for this transformation. Low power architectures
are being developed with mobility in mind along with
making use of the statistical nature of this data.
Tools:
Cadence (Verilog-XL, PKS, Encounter, Virtuoso)
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This
page maintained by: Loc Stewart The Center for
Advanced Computer Studies University of Louisiana at
Lafayette Lafayette, Louisiana, 70503 email:
stewart@cacs.louisiana.edu
This
file was last modified November 4, 2015
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